-- $Id: $
-- File name:   SET_N_SHIFT .vhd
-- Created:     4/6/2011
-- Author:      Brandon Blaine Gardner
-- Lab Section: 337-06
-- Version:     1.0  Initial Design Entry
-- Description: 16-bit set-n-shift register with enable signal.


LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

entity SET_N_SHIFT_16  is
  port
  (
    CLK	         : in  std_logic;
    RST_N        : in  std_logic;
    SHIFT_ENABLE : in  std_logic; -- for shifting out
    SET_ENABLE   : in  std_logic; -- for setting value
    DATA_IN      : in std_logic_vector(15 downto 0);
    SHIFT_OUT    : out std_logic
  );
end SET_N_SHIFT_16 ;

architecture simple_set_n_shift_reg of SET_N_SHIFT_16  is
  signal present_val : std_logic_vector(15 downto 0);
  signal next_val : std_logic_vector(15 downto 0);
  signal next_so, so : std_logic;
  --signal di_int : std_logic_vector(15 downto 0);
  
begin
   
  process (CLK, RST_N)
  begin  -- process
    if( RST_N = '0' )
    then
      present_val <= "0000000000000000";
      so <= '0';    
    elsif ( rising_edge(CLK) ) 
    then
      present_val <= next_val;
      so <= next_so;
    end if; 
  end process;

  -- Next value logic: Shift in to the right when told to
  --next_so <= present_val(14) when (SHIFT_ENABLE = '1') else present_val(15);
  --next_val <= present_val(14 downto 0) & '0' when (SHIFT_ENABLE = '1' and SET_ENABLE = '0') else
  --DATA_IN when (SET_ENABLE = '1' and SHIFT_ENABLE = '0') else present_val;
  
  process( SHIFT_ENABLE, SET_ENABLE, present_val, so, DATA_IN )
  begin
    
    next_so <= present_val(15);
    next_val <= present_val;
    if( SHIFT_ENABLE = '1' ) --and SET_ENABLE = '0' )
    then
      next_so <= present_val(14);
      next_val <= present_val(14 downto 0) & '0';
    elsif( SET_ENABLE = '1' ) --and SHIFT_ENABLE = '1' )
    then
      next_val <= DATA_IN;
    end if;
    
  end process;
  
  -- Input Logic
  --di_int <= DATA_IN;
  
  -- Output Logic
  SHIFT_OUT <= so;
   
end simple_set_n_shift_reg;
